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| a FEATURES Low Noise: 0.3 V p-p 0.1 Hz to 10 Hz Low Nonlinearity: 0.003% (G = 1) High CMRR: 120 dB (G = 1000) Low Offset Voltage: 50 V Low Offset Voltage Drift: 0.5 V/ C Gain Bandwidth Product: 25 MHz Pin Programmable Gains of 1, 10, 100, 1000 Input Protection, Power On-Power Off No External Components Required Internally Compensated MIL-STD-883B and Chips Available 16-Lead Ceramic DIP and SOIC Packages and 20-Terminal Leadless Chip Carriers Available Available in Tape and Reel in Accordance with EIA-481A Standard Standard Military Drawing Also Available PRODUCT DESCRIPTION -INPUT G = 10 G = 100 Precision Instrumentation Amplifier AD524 FUNCTIONAL BLOCK DIAGRAM PROTECTION 4.44k 404 40 G = 1000 20k RG1 RG2 20k 20k 20k REFERENCE +INPUT PROTECTION 20k VOUT Vb 20k SENSE AD524 PRODUCT HIGHLIGHTS The AD524 is a precision monolithic instrumentation amplifier designed for data acquisition applications requiring high accuracy under worst-case operating conditions. An outstanding combination of high linearity, high common mode rejection, low offset voltage drift and low noise makes the AD524 suitable for use in many data acquisition systems. The AD524 has an output offset voltage drift of less than 25 V/C, input offset voltage drift of less than 0.5 V/C, CMR above 90 dB at unity gain (120 dB at G = 1000) and maximum nonlinearity of 0.003% at G = 1. In addition to the outstanding dc specifications, the AD524 also has a 25 kHz gain bandwidth product (G = 1000). To make it suitable for high speed data acquisition systems the AD524 has an output slew rate of 5 V/s and settles in 15 s to 0.01% for gains of 1 to 100. As a complete amplifier the AD524 does not require any external components for fixed gains of 1, 10, 100 and 1000. For other gain settings between 1 and 1000 only a single resistor is required. The AD524 input is fully protected for both power-on and power-off fault conditions. The AD524 IC instrumentation amplifier is available in four different versions of accuracy and operating temperature range. The economical "A" grade, the low drift "B" grade and lower drift, higher linearity "C" grade are specified from -25C to +85C. The "S" grade guarantees performance to specification over the extended temperature range -55C to +125C. Devices are available in 16-lead ceramic DIP and SOIC packages and a 20-terminal leadless chip carrier. 1. The AD524 has guaranteed low offset voltage, offset voltage drift and low noise for precision high gain applications. 2. The AD524 is functionally complete with pin programmable gains of 1, 10, 100 and 1000, and single resistor programmable for any gain. 3. Input and output offset nulling terminals are provided for very high precision applications and to minimize offset voltage changes in gain ranging applications. 4. The AD524 is input protected for both power-on and poweroff fault conditions. 5. The AD524 offers superior dynamic performance with a gain bandwidth product of 25 MHz, full power response of 75 kHz and a settling time of 15 s to 0.01% of a 20 V step (G = 100). REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD524-SPECIFICATIONS (@ V = S 15 V, RL = 2 k Min AD524B Typ and TA = +25 C unless otherwise noted) Max Min AD524C Typ Max Min AD524S Typ Max Units Model GAIN Gain Equation (External Resistor Gain Programming) Gain Range (Pin Programmable) Gain Error1 G=1 G = 10 G = 100 G = 1000 Nonlinearity G=1 G = 10,100 G = 1000 Gain vs. Temperature G=1 G = 10 G = 100 G = 1000 VOLTAGE OFFSET (May be Nulled) Input Offset Voltage vs. Temperature Output Offset Voltage vs. Temperature Offset Referred to the Input vs. Supply G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current vs. Temperature Input Offset Current vs. Temperature INPUT Input Impedance Differential Resistance Differential Capacitance Common-Mode Resistance Common-Mode Capacitance Input Voltage Range Max Differ. Input Linear (V DL) 2 Max Common-Mode Linear (V CM) Common-Mode Rejection dc to 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT RATING VOUT, RL = 2 k DYNAMIC RESPONSE Small Signal - 3 dB G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01%, 20 V Step G = 1 to 100 G = 1000 NOISE Voltage Noise, 1 kHz R.T.I. R.T.O. R.T.I., 0.1 Hz to 10 Hz G=1 G = 10 G = 100, 1000 Current Noise 0.1 Hz to 10 Hz Min AD524A Typ Max 40 , 000 RG + 1 20% 40 , 000 RG + 1 20% 40 , 000 RG + 1 20% 40 , 000 RG + 1 20% 1 to 1000 0.05 0.25 0.5 1 to 1000 0.03 0.15 0.35 1.0 0.005 0.005 0.01 5 10 25 50 100 0.75 3 50 75 95 105 110 50 35 25 15 80 100 110 115 1 to 1000 0.02 0.1 0.25 0.5 0.003 0.003 0.01 5 10 25 50 50 0.5 2.0 25 75 95 105 110 15 10 1 to 1000 0.05 0.25 0.5 2.0 0.01 0.01 0.01 5 10 25 50 100 2.0 3.0 50 % % % % % % % ppm/C ppm/C ppm/C ppm/C V V/C mV V/C dB dB dB dB 50 35 nA pA/C nA pA/C 2.0 0.01 0.01 0.01 5 15 35 100 250 2 5 100 70 85 95 100 100 100 100 100 100 100 100 100 109 10 109 10 10 G 12 V - x VD 2 10 10 9 10 10 9 10 G 12 V - x VD 2 10 10 9 10 10 9 10 G 12 V - x VD 2 10 10 9 10 10 9 10 G 12 V - x VD 2 pF pF V V dB dB dB dB 70 90 100 110 10 75 95 105 115 10 80 100 110 120 10 70 90 100 110 10 V 1 400 150 25 5.0 15 75 1 400 150 25 5.0 15 75 1 400 150 25 5.0 15 75 1 400 150 25 5.0 15 75 MHz kHz kHz kHz V/s s s 7 90 15 2 0.3 60 7 90 15 2 0.3 60 7 90 15 2 0.3 60 7 90 15 2 0.3 60 nV/Hz nVHz V p-p V p-p V p-p pA p-p -2- REV. E AD524 Model SENSE INPUT RIN IIN Voltage Range Gain to Output REFERENCE INPUT RIN IIN Voltage Range Gain to Output TEMPERATURE RANGE Specified Performance Storage POWER SUPPLY Power Supply Range Quiescent Current Min AD524A Typ 20 15 l 40 15 l -25 -65 6 15 3.5 +85 +150 18 5.0 -25 -65 6 15 3.5 Max Min AD524B Typ 20 15 l 40 15 10 1 +85 +150 18 5.0 -25 -65 6 15 3.5 l +85 +150 18 5.0 -55 -65 6 15 3.5 Max Min AD524C Typ 20 15 1 40 15 10 1 +125 +150 18 5.0 Max Min AD524S Typ Max 20 15 l 40 15 Units k 20% A V % k 20% A V % C C V mA 10 10 10 10 10 10 NOTES 1 Does not include effects of external resistor RG. 2 VOL is the maximum differential input voltage at G = 1 for specified nonlinearity. VDL at the maximum = 10 V/G. VD = Actual differential input voltage. Example: G = 10, VD = 0.50. VCM = 12 V - (10/2 x 0.50 V) = 9.5 V. Specification subject to change without notice. All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. REV. E -3- AD524 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 450 mW Input Voltage2 (Either Input Simultaneously) |VIN| + |VS | . . . . . . . . <36 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C (D, E) . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Operating Temperature Range AD524A/B/C . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C AD524S . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Lead Temperature (Soldering 60 secs) . . . . . . . . . . . . +300C NOTES 1 ABSOLUTE MAXIMUM RATINGS l CONNECTION DIAGRAMS Ceramic (D) and SOIC (R) Packages - INPUT 1 + INPUT 2 RG2 3 INPUT NULL 4 16 15 14 RG1 OUTPUT NULL OUTPUT NULL G = 10 SHORT TO RG2 FOR DESIRED GAIN AD524 TOP VIEW 13 INPUT NULL 5 (Not to Scale) 12 G = 100 REFERENCE 6 -VS 7 +VS 8 4 15 11 10 9 G = 1000 SENSE OUTPUT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Max input voltage specification refers to maximum voltage to which either input terminal may be raised with or without device power applied. For example, with 18 volt supplies max V IN is 18 volts, with zero supply voltage max V IN is 36 volts. +VS INPUT OFFSET NULL 5 14 -VS OUTPUT OFFSET NULL METALIZATION PHOTOGRAPH Contact factory for latest dimensions. Dimensions shown in inches and (mm). OUTPUT NULL G = 10 G = 100 G = 1000 11 14 13 12 OUTPUT 15 NULL RG1 16 SENSE 10 9 OUTPUT 8 +VS 0.103 (2.61) -INPUT 1 7 -VS Leadless Chip Carrier OUTPUT NULL OUTPUT NULL G = 10 SHORT TO 16 NC RG2 FOR DESIRED 15 G = 100 GAIN 14 G = 1000 18 17 RG2 INPUT NULL NC INPUT NULL REFERENCE 4 5 6 7 8 9 10 11 12 13 +INPUT -INPUT NC RG1 3 2 1 20 19 AD524 TOP VIEW +INPUT 2 RG2 3 5 4 INPUT INPUT NULL NULL 6 REFERENCE 7 NC OUTPUT SENSE 19 18 -VS +VS NC = NO CONNECT +VS INPUT OFFSET NULL 5 -VS OUTPUT OFFSET NULL 0.170 (4.33) PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE D-16 AND R-16 16-PIN CERAMIC PACKAGES. ORDERING GUIDE Model AD524AD AD524AE AD524AR-16 AD524AR-16-REEL AD524AR-16-REEL7 AD524BD AD524BE AD524CD AD524SD AD524SD/883B 5962-8853901EA* AD524SE/883B AD524SCHIPS * Temperature Ranges -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C -55C to +125C -55C to +125C Package Descriptions 16-Lead Ceramic DIP 20-Terminal Leadless Chip Carrier 16-Lead Gull-Wing SOIC Tape & Reel Packaging 13" Tape & Reel Packaging 7" 16-Lead Ceramic DIP 20-Terminal Leadless Chip Carrier 16-Lead Ceramic DIP 16-Lead Ceramic DIP 16-Lead Ceramic DIP 16-Lead Ceramic DIP 20-Terminal Leadless Chip Carrier Die Package Options D-16 E-20A R-16 D-16 E-20A D-16 D-16 D-16 D-16 E-20A Refer to official DESC drawing for tested specifications. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD524 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. E AD524-Typical Characteristics 20 20 30 OUTPUT VOLTAGE SWING - Vp-p V V OUTPUT VOLTAGE SWING - 15 15 INPUT VOLTAGE - 20 10 +25 C 5 10 10 5 0 0 10 15 5 SUPPLY VOLTAGE - V 20 0 0 5 10 15 SUPPLY VOLTAGE - V 20 0 10 100 1k LOAD RESISTANCE - 10k Figure 1. Input Voltage Range vs. Supply Voltage, G = 1 Figure 2. Output Voltage Swing vs. Supply Voltage Figure 3. Output Voltage Swing vs. Load Resistance 8.0 16 14 40 30 INPUT BIAS CURRENT - nA 0 10 15 5 SUPPLY VOLTAGE - V 20 20 10 0 -10 -20 -30 -40 -75 -25 25 75 TEMPERATURE - C 125 QUIESCENT CURRENT - mA nA INPUT BIAS CURRENT - 0 5 10 15 SUPPLY VOLTAGE - V 20 6.0 12 10 8 6 4 2 0 4.0 2.0 0 Figure 4. Quiescent Current vs. Supply Voltage Figure 5. Input Bias Current vs. Supply Voltage Figure 6. Input Bias Current vs. Temperature 16 14 nA 12 INPUT BIAS CURRENT - 10 8 6 4 2 0 0 5 10 15 INPUT VOLTAGE - V 20 0 1 1000 GAIN - V/V 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 WARM-UP TIME - Minutes 8.0 2 3 4 5 6 100 10 1 VOS FROM FINAL VALUE - V 0 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 7. Input Bias Current vs. Input Voltage Figure 8. Offset Voltage, RTI, Turn On Drift Figure 9. Gain vs. Frequency REV. E -5- AD524 -140 -120 -100 CMRR - dB -80 -60 -40 -20 0 FULL POWER RESPONSE - Vp-p G = 1000 G = 100 G = 10 G=1 30 10.0 G = 1, 10, 100 20 SLEW RATE -V/ s 8.0 6.0 4.0 G = 1000 2.0 10 BANDWIDTH LIMITED G1000 G100 G10 1M 0 1k 0 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M 10k 100k FREQUENCY - Hz 0 1 10 GAIN - V/V 100 1000 Figure 10. CMRR vs. Frequency RTI, Zero to 1k Source Imbalance Figure 11. Large Signal Frequency Response Figure 12. Slew Rate vs. Gain 160 POWER SUPPLY REJECTION - dB POWER SUPPLY REJECTION - dB 140 120 100 80 60 G= 100 0 G= 100 G= 10 160 +VS = 15V dc + 1V p-p SINEWAVE 140 120 100 80 60 40 20 0 10 100 1k 10k FREQUENCY - Hz 100k G= 100 0 G= 100 G= 10 1000 -VS = -15V dc + 1V p-p SINEWAVE 100 VOLT NSD - nV/ Hz G=1 G = 10 10 G = 100, 1000 G = 1000 1 G= 40 20 0 10 1 G= 1 0.1 100 1k 10k FREQUENCY - Hz 100k 1 10 100 1k FREQUENCY - Hz 10k 100k Figure 13. Positive PSRR vs. Frequency Figure 14. Negative PSRR vs. Frequency Figure 15. RTI Noise Spectral Density vs. Gain CURRENT NOISE SPECTRAL DENSITY - fA/ Hz 100k 0.1 - 10Hz 0.1 - 10Hz 10k 1000 100 0 1 10 100 FREQUENCY - Hz 1k 10k VERTICAL SCALE; 1 DIVISION = 5 V VERTICAL SCALE; 1 DIVISION = 0.1 V Figure 16. Input Current Noise vs. Frequency Figure 17. Low Frequency Noise - G = 1 (System Gain = 1000) Figure 18. Low Frequency Noise - G = 1000 (System Gain = 100,000) -6- REV. E AD524 -12 TO +12 1% -8 TO +8 -4 TO +4 OUTPUT STEP - V +4 TO -4 +8 TO -8 1% +12 TO -12 0 5 10 15 SETTLING TIME - s 20 0.1% 0.01% 0.1% 0.01% -8 TO +8 -4 TO +4 OUTPUT STEP - V +4 TO -4 +8 TO -8 1% +12 TO -12 0 5 10 15 SETTLING TIME - s 20 0.1% 0.01% -12 TO +12 1% 0.1% 0.01% Figure 19. Settling Time Gain = 1 Figure 20. Large Signal Pulse Response and Settling Time - G =1 Figure 21. Settling Time Gain = 10 -12 TO +12 1% -8 TO +8 -4 TO +4 OUTPUT STEP - V +4 TO -4 +8 TO -8 1% +12 TO -12 0 5 0.1% 0.01% 0.01% 0.1% 10 15 SETTLING TIME - s 20 Figure 22. Large Signal Pulse Response and Settling Time G = 10 Figure 23. Settling Time Gain = 100 Figure 24. Large Signal Pulse Response and Settling Time G = 100 -12 TO +12 1% -8 TO +8 -4 TO +4 OUTPUT STEP - V +4 TO -4 +8 TO -8 1% +12 TO -12 0 10 20 30 40 50 60 SETTLING TIME - s 70 80 0.1% 0.01% 0.1% 0.01% Figure 25. Settling Time Gain = 1000 Figure 26. Large Signal Pulse Response and Settling Time G = 1000 REV. E -7- AD524 10k 0.01% INPUT 20V p-p 100k 0.1% RG1 G = 10 G = 100 11k 0.1% 1k 0.1% 100 0.1% G = 1000 RG2 +VS 1k 10T 10k 0.1% VOUT AD524 -VS As RG is reduced to increase the programmed gain, the transconductance of the input preamp increases to the transconductance of the input transistors. This has three important advantages. First, this approach allows the circuit to achieve a very high open loop gain of 3 x 108 at a programmed gain of 1000, thus reducing gain-related errors to a negligible 30 ppm. Second, the gain bandwidth product, which is determined by C3 or C4 and the input transconductance, reaches 25 MHz. Third, the input voltage noise reduces to a value determined by the collector current of the input transistors for an RTI noise of 7 nV/Hz at G = 1000. INPUT PROTECTION Figure 27. Settling Time Test Circuit +VS I1 50 A VB I2 50 A R52 20k R53 20k A3 SENSE VO A1 C3 CH2, CH3, CH4 CH1 I3 50 A R57 20k Q1, Q3 RG1 A2 C4 -IN R56 20k 4.44k 404 40 G100 Q2, Q4 RG2 R54 20k R55 20k REFERENCE CH2, CH3, CH4 I4 50 A CH1 As interface amplifiers for data acquisition systems, instrumentation amplifiers are often subjected to input overloads, i.e., voltage levels in excess of the full scale for the selected gain range. At low gains, 10 or less, the gain resistor acts as a current limiting element in series with the inputs. At high gains the lower value of RG will not adequately protect the inputs from excessive currents. Standard practice would be to place series limiting resistors in each input, but to limit input current to below 5 mA with a full differential overload (36 V) would require over 7k of resistance which would add 10 nVHz of noise. To provide both input protection and low noise a special series protect FET was used. A unique FET design was used to provide a bidirectional current limit, thereby, protecting against both positive and negative overloads. Under nonoverload conditions, three channels CH2, CH3, CH4, act as a resistance (1 k) in series with the input as before. During an overload in the positive direction, a fourth channel, CH1, acts as a small resistance (3 k) in series with the gate, which draws only the leakage current, and the FET limits IDSS . When the FET enhances under a negative overload, the gate current must go through the small FET formed by CH1 and when this FET goes into saturation, the gate current is limited and the main FET will go into controlled enhancement. The bidirectional limiting holds the maximum input current to 3 mA over the 36 V range. INPUT OFFSET AND OUTPUT OFFSET +IN G1000 -VS Figure 28 Simplified Circuit of Amplifier; Gain Is Defined as ((R56 + R57)/(RG)) + 1. For a Gain of 1, RG Is an Open Circuit Theory of Operation The AD524 is a monolithic instrumentation amplifier based on the classic 3 op amp circuit. The advantage of monolithic construction is the closely matched components that enhance the performance of the input preamp. The preamp section develops the programmed gain by the use of feedback concepts. The programmed gain is developed by varying the value of RG (smaller values increase the gain) while the feedback forces the collector currents Q1, Q2, Q3 and Q4 to be constant, which impresses the input voltage across RG. Voltage offset specifications are often considered a figure of merit for instrumentation amplifiers. While initial offset may be adjusted to zero, shifts in offset voltage due to temperature variations will cause errors. Intelligent systems can often correct for this factor with an autozero cycle, but there are many smallsignal high-gain applications that don't have this capability. +VS 10 100 1000 RG2 +Vs AD712 1F AD524 DUT 16.2k 1/2 1F G1000 G1, 10, 100 1k 100 1.62M 9.09k 1/2 1F -VS 1.82k 16.2k -VS Figure 29. Noise Test Circuit -8- REV. E AD524 Voltage offset and drift comprise two components each; input and output offset and offset drift. Input offset is that component of offset that is directly proportional to gain i.e., input offset as measured at the output at G = 100 is 100 times greater than at G = 1. Output offset is independent of gain. At low gains, output offset drift is dominant, while at high gains input offset drift dominates. Therefore, the output offset voltage drift is normally specified as drift at G = 1 (where input effects are insignificant), while input offset voltage drift is given by drift specification at a high gain (where output offset effects are negligible). All inputrelated numbers are referred to the input (RTI) which is to say that the effect on the output is "G" times larger. Voltage offset vs. power supply is also specified at one or more gain settings and is also RTI. By separating these errors, one can evaluate the total error independent of the gain setting used. In a given gain configuration both errors can be combined to give a total error referred to the input (R.T.I.) or output (R.T.O.) by the following formula: Total Error R.T.I. = input error + (output error/gain) Total Error R.T.O. = (Gain x input error) + output error As an illustration, a typical AD524 might have a +250 V output offset and a -50 V input offset. In a unity gain configuration, the total output offset would be 200 V or the sum of the two. At a gain of 100, the output offset would be -4.75 mV or: +250 V + 100(-50 V) = -4.75 mV. The AD524 provides for both input and output offset adjustment. This simplifies very high precision applications and minimize offset voltage changes in switched gain applications. In such applications the input offset is adjusted first at the highest programmed gain, then the output offset is adjusted at G = 1. GAIN For best results RG should be a precision resistor with a low temperature coefficient. An external RG affects both gain accuracy and gain drift due to the mismatch between it and the internal thin-film resistors. Gain accuracy is determined by the tolerance of the external RG and the absolute accuracy of the internal resistors (20%). Gain drift is determined by the mismatch of the temperature coefficient of RG and the temperature coefficient of the internal resistors (- 50 ppm/C typ). +VS -INPUT RG1 1.5k 2.105k 1k RG2 +INPUT G= -VS REFERENCE 40,000 +1 = 20 2.105 20% AD524 VOUT Figure 31. Operating Connections for G = 20 The second technique uses the internal resistors in parallel with an external resistor (Figure 32). This technique minimizes the gain adjustment range and reduces the effects of temperature coefficient sensitivity. +VS -INPUT RG1 G = 10 4k RG2 +INPUT *R|G = 10 = 4444.44 *R|G = 100 = 404.04 *R|G = 1000 = 40.04 -VS AD524 VOUT REFERENCE 40,000 +1 = 20 G= 4000||4444.44 17% The AD524 has internal high accuracy pretrimmed resistors for pin programmable gain of 1, 10, 100 and 1000. One of the preset gains can be selected by pin strapping the appropriate gain terminal and RG2 together (for G = 1 RG2 is not connected). +VS INPUT OFFSET NULL 10k RG1 G = 10 G = 100 G = 1000 RG2 +INPUT -VS OUTPUT SIGNAL COMMON *NOMINAL ( 20%) Figure 32. Operating Connections for G = 20, Low Gain T.C. Technique -INPUT AD524 VOUT The AD524 may also be configured to provide gain in the output stage. Figure 33 shows an H pad attenuator connected to the reference and sense lines of the AD524. R1, R2 and R3 should be made as low as possible to minimize the gain variation and reduction of CMRR. Varying R2 will precisely set the gain without affecting CMRR. CMRR is determined by the match of R1 and R3. +VS -INPUT RG1 G = 10 G = 100 G = 1000 RG2 +INPUT G= (R2||40k ) + R1 + R3 (R2||40k ) -VS R3 2.26k (R1 + R2 + R3)||RL 2k R1 2.26k R2 5k RL Figure 30. Operating Connections for G = 100 The AD524 can be configured for gains other than those that are internally preset; there are two methods to do this. The first method uses just an external resistor connected between pins 3 and 16, which programs the gain according to the formula 40k RG = G = -1 (see Figure 31). AD524 VOUT Figure 33. Gain of 2000 REV. E -9- AD524 Table I. Output Gain Resistor Values Output Gain 2 5 10 R2 5 k 1.05 k 1 k R1, R3 2.26 k 2.05 k 4.42 k Nominal Gain 2.02 5.01 10.1 Although instrumentation amplifiers have differential inputs, there must be a return path for the bias currents. If this is not provided, those currents will charge stray capacitances, causing the output to drift uncontrollably or to saturate. Therefore, when amplifying "floating" input sources such as transformers and thermocouples, as well as ac-coupled sources, there must still be a dc path from each input to ground. COMMON-MODE REJECTION INPUT BIAS CURRENTS Input bias currents are those currents necessary to bias the input transistors of a dc amplifier. Bias currents are an additional source of input error and must be considered in a total error budget. The bias currents, when multiplied by the source resistance, appear as an offset voltage. What is of concern in calculating bias current errors is the change in bias current with respect to signal voltage and temperature. Input offset current is the difference between the two input bias currents. The effect of offset current is an input offset voltage whose magnitude is the offset current times the source impedance imbalance. +VS Common-mode rejection is a measure of the change in output voltage when both inputs are changed equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. "Common-Mode Rejection Ratio" (CMRR) is a ratio expression while "CommonMode Rejection" (CMR) is the logarithm of that ratio. For example, a CMRR of 10,000 corresponds to a CMR of 80 dB. In an instrumentation amplifier, ac common-mode rejection is only as good as the differential phase shift. Degradation of ac common-mode rejection is caused by unequal drops across differing track resistances and a differential phase shift due to varied stray capacitances or cable capacitances. In many applications shielded cables are used to minimize noise. This technique can create common mode rejection errors unless the shield is properly driven. Figures 35 and 36 shows active data guards that are configured to improve ac common mode rejection by "bootstrapping" the capacitances of the input cabling, thus minimizing differential phase shift. +VS -INPUT G = 100 100 RG2 AD524 LOAD -VS TO POWER SUPPLY GROUND a. Transformer Coupled +VS AD524 VOUT REFERENCE AD711 +INPUT -VS AD524 LOAD -VS Figure 35. Shield Driver, G 100 TO POWER SUPPLY GROUND -INPUT 100 +VS AD712 RG1 b. Thermocouple +VS AD524 -VS 100 RG2 +INPUT -VS VOUT REFERENCE AD524 Figure 36. Differential Shield Driver LOAD GROUNDING -VS TO POWER SUPPLY GROUND c. AC Coupled Figure 34. Indirect Ground Returns for Bias Currents Many data acquisition components have two or more ground pins that are not connected together within the device. These grounds must be tied together at one point, usually at the system power-supply ground. Ideally, a single solid ground would be desirable. However, since current flows through the ground wires and etch stripes of the circuit cards, and since these paths have resistance and inductance, hundreds of millivolts can be generated between the system ground point and the data -10- REV. E AD524 acquisition components. Separate ground returns should be provided to minimize the current flow in the path from the sensitive points to the system ground point. In this way supply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. Since the output voltage is developed with respect to the potential on the reference terminal, an instrumentation amplifier can solve many grounding problems. REFERENCE TERMINAL The reference terminal may be used to offset the output by up to 10 V. This is useful when the load is "floating" or does not share a ground with the rest of the system. It also provides a direct means of injecting a precise offset. It must be remembered that the total output swing is 10 volts to be shared between signal and reference offset. When the IA is of the three-amplifier configuration it is necessary that nearly zero impedance be presented to the reference terminal. Any significant resistance from the reference terminal to ground increases the gain of the noninverting signal path, thereby upsetting the common-mode rejection of the IA. In the AD524 a reference source resistance will unbalance the CMR trim by the ratio of 20 k/RREF. For example, if the reference source impedance is 1 , CMR will be reduced to 86 dB (20 k/1 = 86 dB). An operational amplifier may be used to provide that low impedance reference point as shown in Figure 39. The input offset voltage characteristics of that amplifier will add directly to the output offset voltage performance of the instrumentation amplifier. +VS SENSE VIN + ANALOG P.S. +15V C -15V DIGITAL P.S. +5V C 0.1 0.1 F F 0.1 0.1 F F DIG COM 1F1F 1F AD524 6 AD583 SAMPLE AND HOLD AD574A DIGITAL DATA OUTPUT OUTPUT REFERENCE *ANALOG GROUND SIGNAL GROUND *IF INDEPENDENT; OTHERWISE RETURN AMPLIFIER REFERENCE TO MECCA AT ANALOG P.S. COMMON Figure 37. Basic Grounding Practice SENSE TERMINAL VIN - AD524 REF LOAD The sense terminal is the feedback point for the instrument amplifier's output amplifier. Normally it is connected to the instrument amplifier output. If heavy load currents are to be drawn through long leads, voltage drops due to current flowing through lead resistance can cause errors. The sense terminal can be wired to the instrument amplifier at the load, thus putting the IxR drops "inside the loop" and virtually eliminating this error source. V+ VIN + (SENSE) OUTPUT CURRENT BOOSTER -VS AD711 VOFFSET Figure 39. Use of Reference Terminal to Provide Output Offset An instrumentation amplifier can be turned into a voltage-tocurrent converter by taking advantage of the sense and reference terminals as shown in Figure 40. SENSE R1 +INPUT AD524 VIN - V- (REF) X1 RL -INPUT AD524 REF A2 VX IL AD711 Figure 38. AD524 Instrumentation Amplifier with Output Current Booster IL = VX VIN = = R1 R1 (1 + 40,000 ) R G LOAD Typically, IC instrumentation amplifiers are rated for a full 10 volt output swing into 2 k. In some applications, however, the need exists to drive more current into heavier loads. Figure 38 shows how a high-current booster may be connected "inside the loop" of an instrumentation amplifier to provide the required current boost without significantly degrading overall performance. Nonlinearities, offset and gain inaccuracies of the buffer are minimized by the loop gain of the IA output amplifier. Offset drift of the buffer is similarly reduced. Figure 40. Voltage-to-Current Converter By establishing a reference at the "low" side of a current setting resistor, an output current may be defined as a function of input voltage, gain and the value of that resistor. Since only a small current is demanded at the input of the buffer amplifier A2, the forced current IL will largely flow through the load. Offset and drift specifications of A2 must be added to the output offset and drift specifications of the IA. REV. E -11- AD524 -IN +IN 1 2 3 PROTECTION PROTECTION +VS 14 4.44k 16 15 R2 10k OUTPUT OFFSET TRIM G = 10 K1 NC G = 100 K2 G = 1000 K3 INPUT OFFSET TRIM R1 10k 4 20k 5 20k 6 20k 20k 40 20k 404 13 12 11 20k RELAY SHIELDS +5V 10 -VS +VS 1F 35V ANALOG COMMON C1 C2 7 8 A1 AD524 OUT 9 K1 D1 K2 D2 K3 D3 K1 - K3 = THERMOSEN DM2C 4.5V COIL D1 - D3 = IN4148 GAIN TABLE A B GAIN 0 0 10 0 1 1000 1 0 100 111 INPUTS A GAIN RANGE B 74LS138 DECODER Y0 Y1 Y2 7407N BUFFER DRIVER 10 F +5V NC = NO CONNECT LOGIC COMMON Figure 41. Three Decade Gain Programmable Amplifier PROGRAMMABLE GAIN Figure 41 shows the AD524 being used as a software programmable gain amplifier. Gain switching can be accomplished with mechanical switches such as DIP switches or reed relays. It should be noted that the "on" resistance of the switch in series with the internal gain resistor becomes part of the gain equation and will have an effect on gain accuracy. The AD524 can also be connected for gain in the output stage. Figure 42 shows an AD711 used as an active attenuator in the output amplifier's feedback loop. The active attenuation presents a very low impedance to the feedback resistors, therefore minimizing the common-mode rejection ratio degradation. -IN +IN (+INPUT) 1 PROTECTION PROTECTION +VS 3 14 4.44k 4 13 20k 5 20k 6 20k 20k 20k 404 40 11 20k 7 10 12 16 15 (-INPUT) 2 INPUT OFFSET NULL OUTPUT OFFSET NULL TO -V R2 10k 10k -VS +VS 1F 35V AD524 8 9 VOUT 20k 10pF +VS 39.2k 1k 1k 1k VSS VDD GND AD711 -VS 28.7k 316k AD7590 VDD A2 A3 A4 WR Figure 42. Programmable Output Gain -12- REV. E AD524 +VS +INPUT (-INPUT) 1 G = 10 13 G = 100 12 G = 1000 11 RG1 16 RG2 3 40 PROTECTION 4.44k 404 Vb 20k 20k 20k 9 20k 20k -INPUT 2 (+INPUT) PROTECTION +VS 17 4 DATA INPUTS CS WR DAC A/DAC B 14 DB0 7 DB7 15 16 6 18 DAC B 5 1 3 DAC A 2 6 -VS VOUT 39k 20k 10 +INPUT RG1 G = 10 G = 100 G = 1000 RG2 -INPUT VREF +VS C1 OUT1 +VS R4 10k -VS R3 20k R5 20k AD524 AD524 AD589 MSB 1/2 AD712 DATA INPUTS LSB CS WR 1/2 AD712 AD7524 OUT2 256:1 1/2 AD712 GND R6 5k -VS AD7528 19 20 Figure 44. Software Controllable Offset 1/2 AD712 Figure 43. Programmable Output Gain Using a DAC In many applications complex software algorithms for autozero applications are not available. For those applications Figure 45 provides a hardware solution. +VS 15 16 14 13 RG2 RG1 8 10 VOUT 0.1 F LOW LEAKAGE 1k -VS 12 11 9 10 CH Another method for developing the switching scheme is to use a DAC. The AD7528 dual DAC, which acts essentially as a pair of switched resistive attenuators having high analog linearity and symmetrical bipolar transmission, is ideal in this application. The multiplying DAC's advantage is that it can handle inputs of either polarity or zero without affecting the programmed gain. The circuit shown uses an AD7528 to set the gain (DAC A) and to perform a fine adjustment (DAC B). AUTOZERO CIRCUITS AD524 AD711 In many applications it is necessary to provide very accurate data in high gain configurations. At room temperature the offset effects can be nulled by the use of offset trimpots. Over the operating temperature range, however, offset nulling becomes a problem. The circuit of Figure 44 show a CMOS DAC operating in the bipolar mode and connected to the reference terminal to provide software controllable offset adjustments. VDD VSS GND 200 s ZERO PULSE A1 A2 A3 A4 AD7510KD Figure 45. Autozero Circuit REV. E -13- AD524 ERROR BUDGET ANALYSIS To illustrate how instrumentation amplifier specifications are applied, we will now examine a typical case where an AD524 is required to amplify the output of an unbalanced transducer. Figure 46 shows a differential transducer, unbalanced by 100 , supplying a 0 to 20 mV signal to an AD524C. The output of the IA feeds a 14-bit A-to-D converter with a 0 to 2 volt input voltage range. The operating temperature range is -25C to +85C. Therefore, the largest change in temperature T within the operating range is from ambient to +85C (85C - 25C = 60C). +10V In many applications, differential linearity and resolution are of prime importance. This would be so in cases where the absolute value of a variable is less important than changes in value. In these applications, only the irreducible errors (45 ppm = 0.004%) are significant. Furthermore, if a system has an intelligent processor monitoring the A-to-D output, the addition of a autogain/autozero cycle will remove all reducible errors and may eliminate the requirement for initial calibration. This will also reduce errors to 0.004%. +VS 10k 350 350 RG1 G = 100 350 350 RG2 14-BIT ADC 0V TO 2V F.S. AD524C -VS Figure 46. Typical Bridge Application Table II. Error Budget Analysis of AD524CD in Bridge Application Error Source Gain Error Gain Instability Gain Nonlinearity Input Offset Voltage Input Offset Voltage Drift AD524C Specifications Calculation 0.25% = 2500 ppm (25 ppm/C)(60C) = 1500 ppm 0.003% = 30 ppm 50 V/20 mV = 2500 ppm ( 0.5 V/C)(60C) = 30 V 30 V/20 mV = 1500 ppm 2.0 mV/20 mV = 1000 ppm ( 25 V/C)(60C)= 1500 V 1500 V/20 mV = 750 ppm ( 15 nA)(100 ) = 1.5 V 1.5 V/20 mV = 75 ppm ( 100 pA/C)(100 )(60C) = 0.6 V 0.6 V/20 mV= 30 ppm ( 10 nA)(100 ) = 1 V 1 V/20 mV = 50 ppm (100 pA/C)(100 )(60C) = 0.6 V 0.6 V/20 mV = 30 ppm (10 nA)(175 ) = 3.5 V 3.5 V/20 mV = 87.5 ppm (100 pA/C)(175 )(60C) = 1 V 1 V/20 mV = 50 ppm 115 dB = 1.8 ppm x 5 V = 8.8 V 8.8 V/20 mV = 444 ppm 0.3 V p-p/20 mV = 15 ppm Total Error Effect on Absolute Accuracy at TA = +25 C 2500 ppm - - 2500 ppm - 1000 ppm - 75 ppm - 50 ppm - 87.5 ppm - 444 ppm - 6656.5 ppm Effect on Absolute Accuracy at TA = +85 C 2500 ppm 1500 ppm - 2500 ppm 1500 ppm 1000 ppm 750 ppm 75 ppm 30 ppm 50 ppm 30 ppm 87.5 ppm 50 ppm 444 ppm - 10516.5 ppm Effect on Resolution - - 30 ppm - - - - - - - - - - - 15 ppm 45 ppm 0.25% 25 ppm 0.003% 50 V, RTI 0.5 V/C - Output Offset Voltage* 2.0 mV Output Offset Voltage Drift* 25 V/C Bias Current-Source Imbalance Error Bias Current-Source Imbalance Drift Offset Current-Source Imbalance Error Offset Current-Source Imbalance Drift Offset Current-Source Resistance-Error Offset Current-Source Resistance-Drift Common Mode Rejection 5 V dc Noise, RTI (0.1 Hz-10 Hz) 15 nA 100 pA/C 10 nA 100 pA/C 10 nA 100 pA/C 115 dB 0.3 V p-p *Output offset voltage and output offset voltage drift are given as RTI figures. -14- REV. E AD524 Figure 47 shows a simple application, in which the variation of the cold-junction voltage of a Type J thermocouple-iron(+)- constantan-is compensated for by a voltage developed in series by the temperature-sensitive output current of an AD590 semiconductor temperature sensor. RA NOMINAL TYPE VALUE J K E T S, R 52.3 41.2 61.4 40.2 5.76 REFERENCE JUNCTION +15 C < TA < +35 C TA VA and the circuit near 25C. If resistors with low tempcos are used, compensation accuracy will be to within 0.5C, for temperatures between +15C and +35C. Other thermocouple types may be accommodated with the standard resistance values shown in the table. For other ranges of ambient temperature, the equation in the figure may be solved for the optimum values of RT and R A. The microprocessor controlled data acquisition system shown in Figure 48 includes both autozero and autogain capability. By dedicating two of the differential inputs, one to ground and one to the A/D reference, the proper program calibration cycles can eliminate both initial accuracy errors and accuracy errors over temperature. The autozero cycle, in this application, converts a number that appears to be ground and then writes that same number (8-bit) to the AD7524, which eliminates the zero error since its output has an inverted scale. The autogain cycle converts the A/D reference and compares it with full scale. A multiplicative correction factor is then computed and applied to subsequent readings. For a comprehensive study of instrumentation amplifier design and applications, refer to the Instrumentation Amplifier Application Guide, available free from Analog Devices. +VS IA 2.5V 7.5V AD580 G = 100 +VS AD590 RA CU 52.3 IA + 2.5V 52.3 1+ R 52.3 EO 8.66k - 2.5V RT 1k AD524 IRON VT CONSTANTAN MEASURING JUNCTION EO = VT - VA + VT -VS OUTPUT AMPLIFIER OR METER NOMINAL VALUE 9135 Figure 47. Cold-Junction Compensation The circuit is calibrated by adjusting RT for proper output voltage with the measuring junction at a known reference temperature RG2 AD583 VREF AD7507 RG1 AD524 VIN AGND -VREF AD574A A0 A2 EN A1 20k 20k 10k AD7524 1/2 AD712 LATCH 5k 1/2 AD712 DECODE CONTROL MICROPROCESSOR ADDRESS ADDRESS BUS BUS Figure 48. Microprocessor Controlled Data Acquisition System REV. E -15- AD524 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Ceramic DIP (D-16) 0.005 (0.13) MIN 16 0.080 (2.03) MAX 9 0.310 (7.87) 0.220 (5.59) 1 8 PIN 1 0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) 0.150 (3.81) MAX SEATING 0.070 (1.78) PLANE 0.030 (0.76) 0.015 (0.38) 0.008 (0.20) 20-Terminal Leadless Chip Carrier (E-20A) 0.100 (2.54) 0.064 (1.63) 0.095 (2.41) 0.075 (1.90) TOP VIEW 0.358 (9.09) MAX SQ 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.075 (1.91) REF 0.200 (5.08) BSC 0.100 (2.54) BSC 3 4 1 0.358 (9.09) 0.342 (8.69) SQ 19 18 20 0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC BOTTOM VIEW 14 13 8 9 45 TYP 0.088 (2.24) 0.054 (1.37) 0.055 (1.40) 0.045 (1.14) 0.150 (3.81) BSC 16-Lead SOIC (R-16) 0.4133 (10.50) 0.3977 (10.00) 16 9 1 8 PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) 0.0500 (1.27) BSC 8 0.0192 (0.49) 0 SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) -16- REV. E PRINTED IN U.S.A. 0.0291 (0.74) x 45 0.0098 (0.25) C722e-0-4/99 |
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